The basic idea of the transistor structure in accordance with the present invention is based on a structure called an IPG, for example, a structure in which a gate controlling a channel comprises a two-dimensional electron gas layer and the like, and the IPG transistor described below is recited in "Applied Physics Letters 1990, Vol. 57, No. 25, pp. 2695 to 2697".
FIG. 21 is a perspective view illustrating a schematic construction of a prior art IPG transistor, FIG. 22(a) is a cross-sectional view of FIG. 21 in line A--A, and FIG. 22(b) is a plan view illustrating a layout of a source, a drain and a gate portion of the IPG transistor. In the IPG transistor 200 shown in the figures, a source region 8 and a drain region 9 are disposed on a semi-insulating GaAs substrate 1 with a predetermined interval therebetween, and a channel portion 4 electrically connecting between these regions is disposed between both the regions.
The source and drain regions 8 and 9 and the channel portion 4 respectively comprise GaAs parts 18, 19, and 14 having a prescribed plane configuration projecting on the substrate 1, and n type AlGaAs layers 28, 29, and 24 disposed on the respective GaAs parts 18, 19, and 14. A quite thin electron conductive layer as about 10 nm thickness called as a two-dimensional electron gas (hereinafter referred to as "2DEG") layer is produced at a portion of each the GaAs part in the vicinity of the interface with the n type AlGaAs layer.
The element structure in which a two-dimensional electron gas layer is produced in a semiconductor layer as described above is fundamentally the same as that used in transistors such as a HEMT (High Electron Mobility Transistor) and an MODFET (Modulation Doped FET), which are generally employed as high performance elements for microwave. The above-described IPG transistor is only different in the structure of the channel portion 4 from the HEMT or the MODFET.
In more detail, in the IPG transistor 200, the channel portion 4 is processed so as to have quite a small width as 0.6 .mu.m as recited in the above-described reference, and the electrons at the electron conductive layer of the channel portion 4 are confined in a further narrower region affected by the surface depletion layers extending from the side surfaces of the channel portion. Therefore, the electrons run in a quasi-one-dimensional fine line region (hereinafter alternatively referred to as a "Q1D conductive channel") at the channel portion 4. FIG. 22(b) shows a flow of an electron e running through the channel portion 4 from the source region 8 toward the drain electrode 9.
Gate portions 5a and 5b are disposed at both sides of the channel portion 4 with predetermined intervals from the channel portion 4. Both the gate portions 5a and 5b comprise GaAs portions 15a and 15b each having a prescribed plane configuration projecting on the substrate 1 and n type AlGaAs layers 25a and 25b disposed on the respective GaAs portions similarly to the channel portion 4. Two-dimensional electron gas layers 7a and 7b are produced at portions of the respective GaAs portions 15a and 15b in the vicinity of the interfaces with the n type AlGaAs layers 25a and 25b. Here, gap grooves 3a and 3b separate the channel portion 4 where a current flows and the gate portions 5a and 5b.
A source electrode 209 and a drain electrode 208 comprising Au-Ge alloy or the like are disposed at the source and drain regions 8 and 9, respectively, and gate electrodes 205a and 205b comprising Au-Ge alloy or the like are disposed on the gate portions 5a and 5b, respectively.
FIG. 23 shows a detailed semiconductor layer structure of the IPG transistor. In the figure, the same reference numerals as those in FIG. 22 designate the same elements. An intrinsic GaAs (hereinafter referred to as "i type GaAs") buffer layer 1a of about 1 .mu.m thickness is produced on the semi-insulating GaAs substrate 1. An i type GaAs active layer 1b of high purity of about 1000 .ANG. (100 nm) thickness is produced on the buffer layer 1a. An i type AlGaAs layer 2a is produced between the i type GaAs layer 1b and an n type AlGaAs layer 2, and the two-dimensional electron gas layers 7a and 7b are produced at portions of the i type GaAs layer 1b in the vicinity of the interface with the i type AlGaAs layer 2a.
In addition, the Au-Ge alloy electrodes 205a and 205b are disposed on the n type AlGaAs layer 2 via a relatively thick n type GaAs layer 2b. The n type GaAs layer 2b is disposed between the Au-Ge alloy electrodes and the n type AlGaAs layer 2 so as to substantially reduce the resistance of the n type AlGaAs layer 2 which is a relatively high resistance as well as to obtain an ohmic contact between the Au-Ge alloy electrodes and the n type AlGaAs layer 2.
The production method will be described below.
First of all, the n type AlGaAs layer 2 into which Si is doped at a high concentration is epitaxially grown on the semi-insulating GaAs substrate 1 as shown in FIG. 24(a). In this state, a thin conductive layer 9 comprising two-dimensional electron gas is produced at a portion of the GaAs substrate 1 in the vicinity of the hetero interface with the n type AlGaAs layer 2.
Here, in the actual production process, the i type GaAs buffer layer 1a, the i type GaAs active layer 1b, and the i type AlGaAs layer 2a into which layers no impurity is doped are successively grown as shown in FIG. 23, but these semiconductor layers are not shown in FIG. 24 because these layers have no relation to the essence of the operation of the device. Thus, while successively laminating a plurality of semiconductor layers, impurity is selectively doped only into a prescribed semiconductor layer, and this is generally called a selective doping method.
Next, a photoresist film 10 is applied on the entire surface as shown in FIG. 24(b), and the photoresist film 10 is patterned by performing exposure and development to the photoresist film 10, thereby producing a photoresist mask 10b as shown in FIG. 24(c). Because a precise dimension control is required in this patterning, a technique of electron beam patterning is employed for producing the exposure pattern, and for this reason, PMMA (Polymethyl Methacylate) having sensitivity against electron beam is employed as the photoresist 10.
Subsequently, the n type AlGaAs layer 2 and the surface portion of the GaAs substrate 1 therebelow are etched vertically by the dry etching technique called RIE (Reactive Ion Etching) using the photoresist mask 10b as a mask, thereby producing the channel portion 4 and the gate portions 5a and 5b as shown in FIG. 24(d).
In other words, as shown in FIG. 24(d), a portion put between the two gap grooves 3a and 3b produced by the above-described etching is the channel portion 4, and the portions confronting via the gap grooves at both sides of the channel portion 4 are the gate portions 5a and 5b. In this state, since the two-dimensional electron gas layer in the channel portion 4 is pushed from both sides by the surface potential of the side surfaces of the channel portion 4 toward the center of the channel portion 4, it has a width of below about 0.2 .mu.m when the width of the channel portion 4 is 0.6 .mu.m as shown in the figure, resulting in that the two-dimensional electron gas layer becomes a quasi-one-dimensional electron system (hereinafter alternatively referred to as Q1DES), i.e., a quasi-one-dimensional conductive channel 6.
Thereafter, the photoresist mask 10b is removed and formation of electrodes and the like are carried out, thereby completing the IPG transistor 200 (refer to FIG. 21 and FIG. 22(a)). Then, the IPG transistor 200 is a depletion type one in which the quasi-one-dimensional conductive channel 6 is produced at the channel portion 4 in a state where no gate voltage is applied to the gate portions 5a and 5b as shown in FIG. 22(a).
The operation of this IPG transistor will be described below.
In the depletion type IPG transistor 200 of the above-described structure, when no gate voltage is applied to the gate portions 5a and 5b, at the portions X1 in the vicinity of the both side end surfaces of the channel portion 4, the potential level at the surface of the GaAs substrate 1 rises up affected by the surface depletion layers as shown in FIG. 25(b), and no two-dimensional electron gas layer is produced, while at the center portion X2 of the channel portion 4, the influences of the surface depletion layers are small, and the channel 6 comprising the two-dimensional electron gas is produced at a portion of the GaAs substrate 1 in the vicinity of the interface with the AlGaAs layer, where the potential level of electron is fallen down as shown in FIG. 25(c). In this state, the IPG transistor 200 is in an on state where the region between the source and drain regions 8 and 9 is electrically connected by the quasi-one-dimensional conductive channel 6.
When a gate voltage is applied to the gate portions 5a and 5b, also at the center portion X2 of the channel portion 4 (refer to FIG. 25(c) and FIG. 26(c)), the potential level at the surface of the GaAs substrate 1 rises up affected by the electric fields from the two-dimensional electron gas layers 7a and 7b of the gate portions 5a and 5b as shown in FIG. 26, similarly to the portions X1 in the vicinity of the both side end surfaces of the channel portion 4 (refer to FIG. 25(b) and FIG. 26(b)), and the potential level at the portion of the GaAs substrate 1 in the vicinity of the interface with the AlGaAs layer where the potential level of electron is fallen down also becomes above the Fermi level E.sub.F, so that the two-dimensional electron gas layer is forfeited as shown in FIG. 26(c). Then, in the IPG transistor 200, the region between the source region 8 and the drain region 9 is electrically isolated and the IPG transistor 200 is in an off state.
As described above, in the quasi-one-dimensional conductive channel 6 produced at the channel portion 4, because the degree of freedom of electron is made one-dimensional, the improvement in the electron mobility similar to the improvement in the electron mobility which has already achieved by making the three-dimensional conductive channel layer of the two-dimensional is expected, and is thought to contribute to the improving the operation speed of the device.
However, the super high speed operation of the IPG transistor is thought to be realized substantially by the reduction in the gate capacitance rather than the above-described improvement in the electron mobility. More concretely, the IPG transistor has the gap grooves 3a and 3b between the channel portion 4 and the gate portions 5a and 5b, so that the channel portion is separated from the gate portions by vacuum regions or regions filled up with air differently from a conventional FET in which those regions comprise semiconductor or dielectric material, therefore the IPG transistor has a low dielectric constant at the region between the channel and the gate and a small gate capacitance as compared with the conventional FET.
Furthermore, because the IPG transistor has the channel comprising the quasi-one-dimensional electron fine line and the gate comprising the two-dimensional electron gas layer, the structure in which a channel and a gate confront to each other is not a structure in which a plane and a plane confront to each other as in the conventional FET, but a structure in which a line and a line confront to each other, resulting in a small gate capacitance.
In the above-described prior art reference, 10 THz is expected as a cut-off frequency of the IPG transistor which is made on trial, and when it is compared with the conventional semiconductor electronic device the cut off frequency is no more than several hundreds GHz. This means an improvement of the operation speed by no less than one column is expected in the IPG transistor.
In addition, in this IPG transistor, because the channel portion is separated from the gate portions by vacuum regions or regions filled up with air, there is an advantage that there is no likelihood of a gate leakage current which is generated in a state where a forward direction voltage is applied to the gate in the conventional GaAs MESFET.
Although in order to increase the mutual conductance (g.sub.m) which is an important performance figure of a transistor, the above-described IPG transistor is required to shorten the interval between the channel and the gate, i.e., the width of the gap grooves 3a and 3b which is about 0.7 .mu.m in the transistor 200, it is not easy to realize using the above-described conventional production method.
In other words, in the conventional dry etching method, it is generally difficult to process an etching groove of a high aspect ratio and when a width of the etching groove is reduced, a depth of the etching is also naturally reduced. In the IPG transistor, when the gap grooves 3a and 3b are shallow, a leakage current flowing through the GaAs substrate between the gate and the channel unfavorably increases, resulting in a problem.
In the conventional IPG transistor described above, because a two-dimensional gas layer is utilized as a gate electrode, a sheet resistance of the two-dimensional electron gas layer comprising AlGaAs/GaAs series material is large as about 1 K.OMEGA., and this results in an obstacle to reducing a parasitic resistance of the gate electrode. In other words, it is necessary to reduce the parasitic resistance for operation of the transistor at a super high speed or at a super high frequency.
Furthermore, in the Q1DES constituting a channel in the IPG transistor, the portion where a current flows is restricted to quite a fine region, so that the current value which can be taken out to the outside in the prior art is very small as about several tens microamperes per one element at the maximum. Electronic circuits at present are usually operated by a current more than several milliamperes with paying consideration on noises or the lime, and for this reason some measure is required to enable its practical use, for example, connecting a plurality of the IPG transistors in parallel with each other at least at a part outputting a signal to the outside so as to increase the output current.